This invention relates to a clock generator having a tunable oscillator and a phase comparator, and to a method of generating a clock signal synchronized with an input signal by comparing the phase of a tunable oscillator with the phase of the signal input.
Network elements of a synchronous digital communications network such as an SDH (synchronous digital hierarchy) or SONET (synchronous optical network) system must be synchronized with a central reference clock which is derived from received message signals. To derive the reference clock signal and perform clock filtering, clock generators are used in each network element of the network. Such a clock generator contains a digital phase-locked loop (PLL), which is locked to an input signal and provides an output signal having the same frequency as the input signal on a long-term basis. A phase-locked loop comprises a tunable oscillator and a phase comparator which compares the input signal with the output signal of the oscillator and provides a resultant output value which is used as a correction signal for tuning the oscillator.
Each interruption of the input signal causes a phase transient in the output signal depending on the control time constant of the PLL. As a result, the average frequency of the output signal is corrupted, particularly in case of frequent short-time interruptions of the input signal. This effect is particularly pronounced in PLLs with edge-triggered phase comparators.